I don't know why, I found that the .v file of the Verilog Test Fixture type used for simulation is displayed in ImplementaTIon. It looks very uncomfortable, but I don't know how to change it. As shown in the figure below, TestDualRam in the red box is a Verilog Test Fixture. Type .v file:
Today, I talked with my buddy and got a solution:
Right click on the file (where the TestDualRam file is located), as shown below:
You can see the value of View AssociaTIon as "All", click the drop-down button on the right, as shown below:
You can see that there are four values ​​to choose from, set the value to SimulaTIon, then OK, and the file will not be displayed in ImplementaTIon.
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