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Fujitsu Microelectronics (Shanghai) Co., Ltd. today announced the launch of two new large-scale integrated circuits (LSIs) that support full HD video (1,920 dots × 1,080 lines) in H.264 format for encoding and decoding. Its lineup in H.264 CODEC LSI products. One of the ultra-low-power chips, the MB86H55, will be the first to introduce a low-power, industry-leading power supply with a total of only 500 mW of internal memory. Samples of the MB86H55 have been available since January 2009. In addition, the upcoming MB86H56 chip can support full HD video (60 frames per second (progressive)) (60p), which can further improve image quality. The MB86H56 sample has been available since April 2009.Thanks to the built-in memory in these two new products, the package is only 15mm × 15mm, making it possible for portable devices (such as digital video cameras), network appliances, commercial broadcast devices and security cameras to record, play and transmit high-definition HD ( HD) Ideal for video.
Digital cameras using the H.264 compression format have become the mainstream in the market. Compared to the previous MPEG-2 compression format, the H.264 compression format can provide longer recording time. Nowadays, after a single charge, the battery with more endurance has become the key to the continuous recording or playback of portable products users. However, as the size of digital cameras continues to shrink, it is no longer possible to continue to use large batteries, making internal components lower power consumption a key requirement.
Since 2007, Fujitsu Microelectronics has begun to supply the MB86H51, a built-in memory that supports full HD H.264 CODEC chips. Now, the new low-power product, the MB86H55, consumes a total of only 500 mW of power in the full HD encoding, including the built-in memory, enabling digital cameras and other portable devices that use the chip to achieve longer continuity. Record and play HD video at the same time while maintaining superb quality.
Fujitsu Microelectronics introduced another MB86H56 CODEC chip that not only continues the high image quality of the current MB86H51, but also supports processing speed of 60 frames per second (progressive scanning), thereby further improving image quality.
Both the new products and the already-released MB86H51 CODEC chips use Fujitsu Lab's proprietary image quality algorithms, which not only achieve high image quality, but also reduce the workload of video processing with high compression technology. With the high recognition of technologies and products in image processing, Fujitsu Microelectronics will continue to strengthen its launch on image and video processing chip products (ASSP).
Sample supply
Product sample
MB86H55 January 2009
MB86H56 April 2009
Sales target: 200,000 pieces per month
Main characteristics
1. Essential elements for portable devices: Two new products, small package and low power consumption, each have a built-in 512Mbit memory (FCRAM). This type of product contains full memory encoding power, including the power consumption of the built-in memory, and its total power consumption is only 500mW (at a processing speed of 30 frames per second). The main reason is: reducing the number of memory chips to be used and adopting Advanced 65nm processing technology. At the same time, these products use a small package with a size of only 15mm × 15mm.
2. Processing speed of 60 frames per second (progressive scan) can further improve image quality (MB86H56)
The current MB86H51 CODEC products process video at 30 frames per second, while the new MB86H56 handles twice as fast as 60 frames per second (progressive scan) (60p) for even better image quality.
3. Both LSIs have built-in scalers for image reduction/reproduction. Both LSIs have built-in scalers for zooming in/out of images. In 16-bit × 32-behavior units, the image can be magnified up to 6 times and the minimum can be reduced to 1/6 times. Therefore, the user can flexibly configure the image quality, resolution, and code stream rate requirements according to their specific applications.
4. Enhanced connectivity to peripheral LSIs to enhance peripheral connectivity of the product, both products have many interfaces. The host interface that can be directly connected to the external CPU bus is a set of 16-bit wide parallel interfaces; a set of TS interfaces can be used as a video interface. In addition, the serial interface can greatly reduce the number of pins on the host interface; similarly, the PCI interface can be easily connected to a PC or a video recorder. Further, by connecting to the external ROM, it is possible to realize high-speed reading in a device using the LSI.
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