With the rapid growth of smartphones and the Internet of Things (IoT), chip power consumption has become a critical concern in recent years. To meet the demands of low-power integrated circuits, it's essential to implement power-efficient design strategies from the very beginning of the system design phase. As the design process advances into the back-end stage, the options for reducing power consumption become more limited, and the efficiency of each method tends to decrease.
Chip power consumption is primarily divided into two components: static leakage power and dynamic power. Static power occurs when the circuit is idle or inactive, caused by various leakage currents such as reverse-biased diode leakage, gate-induced drain leakage, subthreshold leakage, and gate leakage. Dynamic power, on the other hand, arises from the switching activity of transistors, including both switching power due to current flow and short-circuit power during transitions.
In the digital back-end phase, there are several techniques to reduce these power consumptions. One of the most effective methods is the Multi-Supply Multi-Voltage (MSMV) technology. This approach divides the chip into different voltage domains, also known as power domains. Each domain can be powered independently, allowing high-performance sections to operate at higher voltages while lower-performance areas can run at lower voltages, or even be powered off entirely using power gating.
Creating these voltage domains requires careful planning and the use of a unified power constraint file, typically defined with UPF (Unified Power Format). This file plays a crucial role throughout the chip development process, from the front-end gate-level netlist to final logic verification. In the next few articles, we'll dive deeper into how UPF is used in low-power design.
For example, let’s consider a simple MSMV design with three voltage domains: VA_top, VA1, and VA2. The first step is to define the voltage areas:
- `create_power_domain VA_top -include_scope default voltage area`
- `create_power_domain VA1 -elements iA VA1`
- `create_power_domain VA2 -elements iB VA2`
Next, we establish the power supply connections for the default voltage area:
- `create_supply_net VDD`
- `create_supply_port VDD`
- `connect_supply_net VDD -port VDD`
- Repeat similar steps for VDD1 and VSS.
Then, we define the power connections between the different voltage domains:
- `create_supply_port VDD_sw -domain VA1`
- `create_supply_port VDD1_sw -domain VA2`
- `create_supply_port VSS -reuse -domain VA1`
- `create_supply_port VSS -reuse -domain VA2`
- Define corresponding supply nets and connect them accordingly.
Finally, we create power supply sets and associate them with the respective voltage domains:
- `create_supply_set ss_top -function {power VDD} -function {ground VSS}`
- `create_supply_set ss_pd1 -function {power VDD_sw} -function {ground VSS}`
- `create_supply_set ss_pd2 -function {power VDD1_sw} -function {ground VSS}`
- `associate_supply_set ss_top -handle VA_top.primary`
- `associate_supply_set ss_pd1 -handle VA1.primary`
- `associate_supply_set ss_pd2 -handle VA2.primary`
Once the UPF file is properly defined and loaded, the voltage domains will be visible in the GUI, providing a clear visual representation of the power architecture. This step is crucial for ensuring that the power design meets all the required specifications and constraints.
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