With the growing popularity of smartphones and the Internet of Things (IoT), chip power consumption has become a critical concern in recent years. To meet low-power design goals for integrated circuits, it is essential to implement power-saving strategies during the system design phase. As the design process progresses, especially during the back-end stage, the opportunities for further power reduction become more limited, and the percentage of power saved tends to decrease significantly.
The main components of chip power consumption are static leakage power and dynamic power. Static power arises from leakage currents when the circuit is idle or inactive, including reverse-biased diode leakage, gate-induced drain leakage, subthreshold leakage, and gate leakage. Dynamic power, on the other hand, results from transistor transitions and includes switching power due to current flow and short-circuit power caused by temporary current paths. These concepts are typically covered in detail in specialized reference books, so we won't go into too much depth here.
Now, let’s explore how to reduce power consumption during the digital back-end phase.
One of the key solutions is the Multi-Supply Multi-Voltage (MSMV) technique. This method effectively reduces dynamic power by dividing the chip into different voltage regions, also known as Power Domains. Each domain can operate at a different voltage level depending on its function. High-performance modules, such as a CPU, can be placed in a high-voltage domain to maintain speed, while lower-performance modules like USB interfaces can be assigned to a lower voltage domain. Some non-critical modules can even be powered off using Power Gating, which brings their power consumption close to zero.
So, how do we create these Voltage Areas?
First, we need a unified power constraint file, often defined using UPF (Unified Power Format). This file is used throughout the entire chip development process, from the front-end gate-level netlist to final logic verification. In the next few articles, we will dive deeper into UPF and how it helps implement low-power designs.
For example, let's consider a simple MSMV design with three Voltage Areas: VA1, VA2, and a default VA_top.
1. **Define the Voltage Area Information**
- `create_power_domain VA_top –include_scope default voltage area`
- `create_power_domain VA1 –elements iA VA1`
- `create_power_domain VA2 –elements iB VA2`
2. **Create Supply Connections for the Default Voltage Area**
- `create_supply_net VDD`
- `create_supply_port VDD`
- `connect_supply_net VDD -port VDD`
- Repeat similar steps for VDD1 and VSS.
3. **Establish Power Connections Between VA1 and VA2**
- Define supply ports for each domain and connect them accordingly.
4. **Create and Associate Power Sets with the Voltage Areas**
- Define power sets for each domain and associate them with the respective voltage areas.
Once the UPF file is properly defined, you can visualize the voltage areas through the GUI, making it easier to manage and verify the power domains during the design process.
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