Recently, at the Hot Chips conference in California, Baidu unveiled the XPU, a 256-core FPGA-based cloud computing acceleration chip developed in collaboration with Xilinx. This marked one of the first detailed public presentations of the chip's architecture. Baidu has been making significant progress in deep learning, particularly using GPU-based systems. However, the company is now exploring new options to enhance performance and efficiency, leading to the development of the XPU.
Baidu explains the situation of AI and data analysis workloads on FPGA
Baidu researcher Ouyang Jian explained that the XPU was designed with diversity in mind, focusing on computationally intensive and rule-based tasks while ensuring high efficiency, performance, and flexibility. At the Hot Chips conference, he presented the XPU alongside Xilinx, highlighting its potential in handling complex computing workloads.
The XPU aims to strike a balance between performance and efficiency, especially for diverse computing tasks. While FPGAs are excellent for specific applications, their complexity and lack of programmability can be a challenge. In contrast, CPUs offer flexibility, and GPUs excel in parallel processing. The XPU combines the best of these worlds, targeting compute-heavy, rule-based tasks with CPU-like adaptability.
Currently, one of the main challenges with XPU is its limited programmability. Unlike traditional processors, it doesn’t have a compiler yet. Ouyang Jian mentioned that the team is working on developing one, which will make the chip more accessible to developers.
To support tasks like matrix operations and convolutions, XPU features high-bandwidth memory interfaces, including DDR4 and HBM, along with on-chip SRAM for low-latency access. The DSP units within the FPGA provide parallel processing capabilities, enhancing overall performance.
In microbenchmark tests, the XPU showed efficiency comparable to x86 cores for memory-intensive, conventional computing tasks. For tasks requiring data synchronization, scalability still needs improvement. However, for non-synchronized tasks, the XPU scales linearly with the number of cores.
One of the key limitations remains the lack of a compiler, forcing developers to use assembly language and manage execution through the host system. Tasks must be split, coded, and executed via custom logic functions on Linux. This process is still quite involved and not as user-friendly as traditional programming environments.
The XPU features 256 cores operating at 600MHz, with shared memory for efficient data synchronization across all cores. Ouyang Jian emphasized that Baidu has long used FPGAs in its data centers, cloud platforms, and autonomous driving projects. Based on this experience, the company aimed to build a more versatile and powerful solution with the XPU.
Last year, reports emerged about Baidu’s SQL accelerator based on its deep learning SDA. According to Ouyang Jian, the XPU shares similar advantages in terms of memory bandwidth and latency, thanks to its SA architecture.
Although the benchmark results shown were limited, this was the first time Baidu publicly demonstrated the XPU. If the chip proves effective in AI, data analytics, cloud computing, and autonomous driving, Baidu may consider transitioning from FPGA to ASIC technology for future iterations.
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